Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHi,
In the above link, the example uses the Mentor Graphics* Master bus functional model (BFM) to model the HPS AXI Bridge interface communicating with the FPGA core logic. Which required License kindly check the below link table-1 to generate the required(AXI BFM) license and try to simulate. https://www.altera.com/products/intellectual-property/design/ip-base-suite.html Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)