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New ContributorTSE Configuration with phy chip
Hello there,
im working on Ethernet with nios and msgdma but im not sure if my register configuration is correct and currently i had i problem that the data is received to the transmit of the TSE IP but the ether IP is not sending it to chip or the chip received the data but never transmitted over the cable.
I used the configuration that bean mentioned in the ethernet IP catalog and for the chip configuration i used the one that suggested by intel as well.
the board im using is cyclone 10 GX FPGA Development Kit
this is the code for ethernet configuration and chip configuration im using MDIO and LVDS for the connection.
*(tse + 0x10) = 0x00;
*(tse + 0xA0) = 0x1140;
*(tse + 0xA9) = 0x0F00;
*(tse + 0xA0) = 0x9140;
while ( *(tse + 0xA0) != ( 0x1140 ) ) printf("Setting the resetPHY1\n");
while ( *(tse + 0xA1) != ( 0x796D ) ) printf("Setting the resetPHY\n");
//Set Link timer to 1.6ms for SGMII
*(tse + 0x92) = 0x0D40;
*(tse + 0x93) = 0x03;
//Enable SGMII Interface and Enable SGMII Auto Negotiation
//SGMII_ENA = 1, USE_SGMII_AN = 1
*(tse + 0x94) = 0x0003;
//Enable Auto Negotiation
//AUTO_NEGOTIATION_ENA = 1, Bit 6,8,13 can be ignore
*(tse + 0x80) = 0x1140;
*(tse + 0x80) = 0x9140;
while ( *(tse + 0x80) != ( 0x1140 ) ) printf("Setting the resetPCS\n");
while ( *(tse + 0x81) != ( 0xAD ) ) printf("Setting the resetPCS\n");
*(tse + 0x02) = 0x00802220;
while ( *(tse + 0x02) != 0x00802220);
//MAC FIFO Configuration
*(tse + 0x09) = TSE_TRANSMIT_FIFO_DEPTH-16;//tx_section_empty
*(tse + 0x0E ) = 0x03;//tx_almost_full
*(tse + 0x0D ) = 0x08;//tx_almost_empty
*(tse + 0x07 ) = TSE_RECEIVE_FIFO_DEPTH-16;//rx_section_empty
*(tse + 0x0C ) = 0x08;//rx_almost_full
*(tse + 0x0B ) = 0x08;//rx_almost_empty
*(tse + 0x0A ) = 0x10;//tx_section_full
*(tse + 0x08 ) = 0x10;//rx_section_full
// Initialize the MAC address
*(tse + 0x03) = 0x17231C00;
*(tse + 0x04) = 0x0000CB4A;
// MAC function configuration
*(tse + 0x05) = 1518;//frame length
*(tse + 0x17) = 12;//tx_ipg_length
*(tse + 0x06) = 0xFFFF;//pause_quanta
*(tse + 0x02) = 0x00800220;//config register
// Software reset the PHY chip and wait
*(tse + 0x02) = 0x00802220;
while ( *(tse + 0x02) != ( 0x00800220 ) ) printf("Setting the reset\n");
//Enable read and write transfers
*(tse + 0x02) = 0x00800223;
while ( *(tse + 0x02) != 0x00800223 );
and this is a photo that show that the data is transmitted to the transmit of the ethernet
