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Altera_Forum
Honored Contributor
Honored ContributorTrying to make ALTPLL block working for me.
Hello, The question relates with using the ALTPLL core and Quartus II I have inherited a Verilog design. In this design I see they have used altpll core. The input clock of the altpll...
Altera_ForumHonored Contributor
Honored ContributorProblem solved.
The PLL in this design was reconfigured on the fly and this was something I was missing.
