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Altera_Forum
Honored Contributor
15 years agotruncated value
Hi all, when I'm designing a simple mux: assign cmp_b = sel_ab1 ? (n+1'b1) : a; where N = 2 I got this warning: "Warning (10230): Verilog HDL assignment warning at determining...
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- should I redefine as: parameter N = 4'b0010 ? --- Quote End --- Right. Then: assign cmp_b = sel_ab1 ? (N+4'b0001) : a; However these type of warnings are usually not a problem, provided you are aware of the size mismatch and its implications. The compiler will truncate extra bits or pad with zero when missing (i.e. your "+ 1'b1" assignment on a 4bit value would be automatically converted into "+ 4'b0000") Regards