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Altera_Forum's avatar
Altera_Forum
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15 years ago

truncated value

Hi all, when I'm designing a simple mux: assign cmp_b = sel_ab1 ? (n+1'b1) : a; where N = 2 I got this warning: "Warning (10230): Verilog HDL assignment warning at determining...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I presume cmp_b and a are 32 bits wide.

Change the adder to match 32bits:

assign cmp_b = sel_ab1 ? (N+32'h00000001) : a;

You may need to modify N width, too.