Tricking Quartus into Receiving an LVDS Input on a 3.3V TTL Bank of a Stratix III

I'm wondering if there is a way of tricking Quartus into allowing an LVDS input on a 3.3V TTL Bank of a Stratix III?

We mistakenly wired an LVDS output clock from an ADC to a pair or 3.3V TTL inputs on a Stratix III FPGA. The pair of TTL inputs were chosen so that they could be the front end of a differential LVDS receiver if the I/O bank was powered with 2.5V (VCCIO). However, it is powered at 3.3V, which according to Altera documentation (p7-4, see link below) is not compatible with the LVDS standard.

Our question is: is there any way to trick Quartus II into letting us receive an LVDS signal on a 3.3V bank? It occurred to us that we might try to trick Quartus by telling it that the bank is connected to VCCIO=2.5V. Quartus would then let me designate the pins as LVDS in the Pin Assignment Editor. However, the supply would remain at 3.3V -- so my belief is that this wouldn't actually allow the FPGA to read the LVDS signal. Is this right?

Any other suggestions would be appreciated.

Stratix III I/O Handbook:

http://www.altera.com/literature/hb/stx3/stx3_siii5v1_02.pdf