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Altera_Forum
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16 years ago

Tricking Quartus into Receiving an LVDS Input on a 3.3V TTL Bank of a Stratix III

I'm wondering if there is a way of tricking Quartus into allowing an LVDS input on a 3.3V TTL Bank of a Stratix III? We mistakenly wired an LVDS output clock from an ADC to a pair or 3.3V TTL i...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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so my belief is that this wouldn't actually allow the FPGA to read the LVDS signal. Is this right?

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I assume that the LVDS receiver will work, but with reduced performance. But I didn't try. I've been using faked VCCIO settings for other reasons, e.g. as a workaround for Quartus bugs.