tri-state

out_pin : out std_logic; -- is the pin of the fgpa (shall be put in the entity)

signal out_signal, ena : std_logic; -- are internal signal

with ena select

out_pin <= out_signal when 1,

'Z' when others;

In this case ena is active low and is the equivalent of your output enable, when active outpin takes the signal that you want to put out on the pin, whereas when 0 it put it in tri-state.

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I am looking for a Verilog equivalent of a tr-state device (chip-select) on the output pin of my FPGA. I only want to drive a multi-drop bus when selected and go high-impedance when not. What is the easiest way to accomplish this?

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Hi,

you can do it in this way:

module tri_state_test ( in, ena, out);

input in;

input ena;

output out;

assign out = (ena) ? in : 1'bz;

endmodule

Kind regards

GPK

thanks for the response!

I also found the primitive buffif0. Looks like there are few possibilities.