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SDavi9's avatar
SDavi9
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Tri-state bus data bus delayed

I have a design where my data bus is tri-stated and everything seems to work correctly till the tri-state buffer. For some reason the output of the tri-state buffer is delayed by a clock from the inp...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Sure. I'll wait for the updated file.


Thanks,

Best Regards,

Sheng