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SDavi9's avatar
SDavi9
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Tri-state bus data bus delayed

I have a design where my data bus is tri-stated and everything seems to work correctly till the tri-state buffer. For some reason the output of the tri-state buffer is delayed by a clock from the inp...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

I just compiled the original code you provided and didn't make any change to the code (check previously attached test.qar). Then I got the first image result where there is no register between Mux and the IO_OBUF. (May be you have use usbDmuxOUT in any clock process and didn't provide that part of code I'm not sure)

By commenting out the usbCLK'event (elsif usbCLK = '1' /*and usbCLK'event*/ then) in FT601niosWRITEsm is just to show you that's possible to make the clocked register disappear.