Tri-state bus data bus delayed

Dear Sheng,

Thank you so much for all your help.

In the first image that you showed above, as you indicated, there is no register between Mux and the IO_OBUF as there is in my design shown in the image below

"But one thing can be confirmed that clocked register is because of the clock rising-edge trigger condition in process block. For example, by commenting out the usbCLK'event (elsif usbCLK = '1' /*and usbCLK'event*/ then) in FT601niosWRITEsm. I'm getting the technology map viewer result changes below (image)"

I see that from the Technology Map Viewer images that you show that the registers of the state machine have disappeared. However isn't this expected when you remove the clock from a clocked process that builds a statement machine - all the registers will be removed ? Also, the registers that disappeared are within the state machine block - it is not the register that I see that is implemented in the figure above associated with my tri state buffer ?

I expanded my Technology Map View of the write state machine as below and got the following :-

I am pretty sure that all the registers there will also disappear if I comment out the Clock in the clock process ?!

Bests regards

Shmuel