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SDavi9
Occasional Contributor
Occasional ContributorTri-state bus data bus delayed
I have a design where my data bus is tri-stated and everything seems to work correctly till the tri-state buffer. For some reason the output of the tri-state buffer is delayed by a clock from the inp...
ShengN_altera
Super Contributor
Super ContributorHi shmuel,
That clocked register is due to rising-edge triggered of clocked process. For example implementing a Rising Edge D Flip Flop check the code and technology map viewer images below:
If commented out if(rising_edge(Clk)) then, the clocked register is no more visible check images below:
In technology map viewer, at clocked register, you can Locate Node -> Locate in Design File
Thanks,
Best regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.
