Forum Discussion
SDavi9
Occasional Contributor
Occasional ContributorTri-state bus data bus delayed
I have a design where my data bus is tri-stated and everything seems to work correctly till the tri-state buffer. For some reason the output of the tri-state buffer is delayed by a clock from the inp...
sstrell
Super Contributor
Super ContributorCan you repost your code in a little bit easier to read format?
Clocked registers don't get magically added to a combinatorial design. There must be other code (an IP?) that has a clocked process that might be causing this.
SDavi9So I have attached a file that represents all the parts of my code that do the writes to the usbD bidirectional data bus.
