Tri-state bus data bus delayed

Thanks for your reply,

So below is the VHDL code at the upper level

Signal usbDmuxOUT, usbDreadSMout_withbufferedZEROES :std_logic_vector(31 downto 0);

.....

usbDreadSMout is my "read cycle" output data from an internal state machine defined as :-

usbDreadSMout :out std_logic_vector(7 downto 0);

......

usbDreadCYCLEchanSELen is my open enable for usbDreadSMout from the same internal state machine

......

usbDWRSMout is my "write cycle" output data from an internal state machine defined as :-

usbDWRSMout :out std_logic_vector(31 downto 0);

......

usbDen is my open enable for usbDWRSMout from the same internal state machine

My Bi-directional bus USBD [ usbDWRSMout :out std_logic_vector(31 downto 0); ] is implemented as follows :-

usbDreadSMout_withbufferedZEROES(7 downto 0) <= usbDreadSMout; -- DEBUG USB429
usbDreadSMout_withbufferedZEROES(31 downto <= (others => '0'); -- DEBUG USB429

usbDmuxOUT <= usbDreadSMout_withbufferedZEROES when usbDreadCYCLEchanSELen = '1' else usbDWRSMout; -- DEBUG USB429

USBD <= usbDmuxOUT when usbDen = '1' or usbDreadCYCLEchanSELen = '1' else (others => 'Z');

Below I have attached the RTL implementation of the above