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Occasional ContributorTri-state bus data bus delayed
Super ContributorHello,
I presume, Technology Map Viewer shows the gate level implementation.
By the way, now you are talking about clock, previously it sounds like the "delay" occors in pure combinational circuit. It's probably better to show an exact implementation.
Regards
Frank
Occasional ContributorThanks for your reply,
So below is the VHDL code at the upper level
Signal usbDmuxOUT, usbDreadSMout_withbufferedZEROES :std_logic_vector(31 downto 0);
.....
usbDreadSMout is my "read cycle" output data from an internal state machine defined as :-
usbDreadSMout :out std_logic_vector(7 downto 0);
......
usbDreadCYCLEchanSELen is my open enable for usbDreadSMout from the same internal state machine
......
usbDWRSMout is my "write cycle" output data from an internal state machine defined as :-
usbDWRSMout :out std_logic_vector(31 downto 0);
......
usbDen is my open enable for usbDWRSMout from the same internal state machine
My Bi-directional bus USBD [ usbDWRSMout :out std_logic_vector(31 downto 0); ] is implemented as follows :-
usbDreadSMout_withbufferedZEROES(7 downto 0) <= usbDreadSMout; -- DEBUG USB429
usbDreadSMout_withbufferedZEROES(31 downto
usbDmuxOUT <= usbDreadSMout_withbufferedZEROES when usbDreadCYCLEchanSELen = '1' else usbDWRSMout; -- DEBUG USB429
USBD <= usbDmuxOUT when usbDen = '1' or usbDreadCYCLEchanSELen = '1' else (others => 'Z');
Below I have attached the RTL implementation of the above
- SDavi9
Below I have added a shot of the Technology Map Viewer and in fact there does appear to be a latch on the usbDmuxOUT signals for some reason ???
- SDavi9
And in fact when I clicked on one of these Latches and asked for its location in the RTL view I in fact got the following
