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Occasional ContributorTri-state bus data bus delayed
Regular ContributorYou don't say what version of Quartus or even what device you are using. Or if your tr-state bus is on chip or off chip.
That being said, physically any FPGA I am aware of does not have a true on-chip tri-state bus per se, but it is implemented with logic and multiplexors.
So logically your Verilog/VHDL may be written as a tri-state bus, but during synthesis it is turned into logic, specifically an N:1 multiplexor for the driver function.
Depending on how wide your N:1 mux is (ie, number of discrete source drivers) and how fast your clock rate is, it might just be the logic delay is longer than a clock cycle.
Occasional ContributorWe are using Quartus 15.1. FPGA: Cyclone V GX (5CGXFC4F7M11I7) and the 32 bit tri-state bus is implemented on chip and is created by a simple standard VHDL code that is instantiated in my top level design. The output of the tri-state buffer feeds directly into the bi-directional data bus. The bi-directional bus is also feed back into the design where it is clocked\latched along with the control signals to catch the read data for the read cycle process. Note my clock is 100Mhz !
Your answer that the tri-state bus in synthesis is turned into N:1 multiplexor is interesting. Besides shifting my data earlier by a clock - is there anything else I can do to fix this ?
Also this current design is based upon an earlier design from a different chip (Cyclone V 5CEFA7U19I7N) where this issue was not seen ????
I looked at the RTL of the design and a very clear straight forward tri-state buffer was created as expected. Is there another level for synthesis that changes this tri-state buffer into the N:1 multiplexor that you mentioned ? Is there anyway to view this ?
Thank you once again for all your help
Shmuel Davis
