Transceiver Toolkit Design Example

A few clarifying notes ...

1 - altgx does not exist for Stratix V. Transceiver usage in the example design is through Custom PHY IP.

2 - ALTGX_RECONFIG doe snot exist for Stratix V. The new IP block is "alt_xcvr_reconfig" or "Transceiver Reconfiguration Controller".

3 - The PHY IP does contain an embedded reset controller. The user does not manually control the reset sequence of the transceiver.

It sounds like the PLL is not locking. Your first objective would be to ensure that the PLL is getting a proper reference clock. Check your pin assignments and refclk frequency inputs.

Jake