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I tried implementing the second Stratix V example (4-channel 6.443 Gbps links) and this one is transmitting, but the PLL isn't locking.
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Be a little more specific please. If its transmitting, then the TX PLL must be working. So its the receiver PLL that is not locking?
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Based on what I read in the "Transceiver Reset Control in Stratix V Devices" handbook, the transceiver block is being reset properly, and the tx_ready and reconfig_busy status pins are showing 1 and 0 respectively as expected. But pll_locked and rx_ready are both 0.
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Study the document carefully. Some of the signals are for the transmitter block, other are for the receiver block. There are also reset controls that you might need to deassert.
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I tries simulating the file in Modelsim, but I ran into this fatal error -
http://www.altera.com/support/kdb/solutions/spr376737.html Sadly there doesn't seem to be any workarounds
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Try creating the component in Verilog rather than VHDL. Perhaps that works? Or use Modelsim-SE full edition if you have access to a license.
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Any other ways I can figure out why the PLL isn't locking?
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Which PLL first?
The receiver PLLs need to be connected to a reference clock and started in lock-to-reference mode. Then once data is present on the input and toggling, the receiver PLL can transition to lock-to-data mode. This transition can be configured to be automatic.
Cheers,
Dave
Honored Contributor
