Transceiver Toolkit Design Example

Thanks for the help, Dave.

I tried implementing the second Stratix V example (4-channel 6.443 Gbps links) and this one is transmitting, but the PLL isn't locking.

Based on what I read in the "Transceiver Reset Control in Stratix V Devices" handbook, the transceiver block is being reset properly, and the tx_ready and reconfig_busy status pins are showing 1 and 0 respectively as expected. But pll_locked and rx_ready are both 0.

The PLL clock appears to be working according to Signal Tap, and I'm able to measure its frequency by connecting a scope to the associated trigger, and it appears to be 644.53 MHz, as expected.

I tries simulating the file in Modelsim, but I ran into this fatal error - http://www.altera.com/support/kdb/solutions/spr376737.html

Sadly there doesn't seem to be any workarounds

Any other ways I can figure out why the PLL isn't locking?