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What does the line 'Reset Counter to give active high reset to enable offset cancellation' mean?
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The Stratix IV handbook, and I would guess the Stratix V handbook, discuss the initialization sequence for the transceiver blocks. Enabling the transceivers involves allowing for the input offset voltage calibration to complete, PLLs to lock, and the sequencing of analog and digital reset controls. Your only solution is to sit down and read the handbook.
However, while you do this, you can cheat a little. Create a simple system with a few GPIOs and connect those GPIOs to the transceiver block controls (eg., an SOPC system with a JTAG-to-Avalon-MM bridge and a PIO). Then in software toggle each signal while using SignalTap to capture the status bits from the transceiver block. Use that to understand what happens in the hardware. Then in parallel, create a Modelsim testbench and implement similar control signal sequences. You will see that the Modelsim model produces a different result - usually a much faster time for a status bit to change state - but overall the same sequence will occur.
Write your own reset controller to implement the appropriate sequence; use a counter to wait for the 'expected' status signal assertions, use generics to change the values for simulation via hardware, use timeout counts, so that you can generate your own status outputs (eg., PLL did not lock due to missing clock, or missing input cable).
I'm kind-of surprised that Altera just doesn't supply an IP block to implement the correct reset sequencer. But, they don't, and their example code is not always that great, so shrug your shoulders, roll up your sleeves, and write it yourself.
This is probably not what you wanted to hear, but it'll help you get things working.
Cheers,
Dave
Honored Contributor
