Transceiver Toolkit Design Example

Thanks for the tip, I used SignalTap to analyze the test example and found that the system is being held in reset. But I don't understand the purpose of the code that does so:

   wire            system_reset_cnt;
   reg                  system_reset=1'b0;    
    
    // Reset Counter to give active high reset to enable offset cancellation
    counter_128 cnt_128_isnt (
        .clock    (C100mhz),
        .q        (system_reset_cnt)
    );
    always @ (posedge C100mhz)
    begin
       if (system_reset_cnt >= 8'd128)
           begin
              system_reset <= 1'b1;
           end      
    end