Transceiver Toolkit Design Example

First check that the transmitter and receiver are being enabled. There is a very specific reset sequence required on the Stratix IV devices, and I assume there is a similar requirement for the Stratix V devices. For example, check the PLLs are locked. Use SignalTap to probe the enables, status bits, lock bits etc. Use it to become familiar with the IP.

You can then use SignalTap to probe the transmitter parallel output data (with respect to the parallel output data clock), and then another instance to probe the receiver parallel input data.

At least then you can see whether you have sane data leaving the transmitter and nothing or something coming in the receiver.

Cheers,

Dave