Transceiver Rate Match FIFO - Why is it needed?

I am using the custom phy IP (Cyclone V SX ) and had opted for the "automatic state machine", rate matched FIFO, 8b/10b, byte ordering. I setup the design in the QUARTUSII environment ( not in QSYS ). The design always works when performing an external and internal loop-back test ( even through a foot of backplane :)) , if I disconnect, it recovers ( I love that automatic state machine ) without any issues.

The problem arises when I communicate with another module ( which has the same exact PHY design ). The rate matched FIFO detects the small variations in the clock between the TX from module and the RX from the other, and starts to perform its function of deleting and inserting symbols. Since, I opted for byte ordering; the byte order is be lost due to the Rate matched Fifo's inserting and deleting. And my error counter then goes up to 95% error receive rate. There is a note in the XCVR manual that byte ordering is compromised by the Rate matched FIFO.

So, I removed the Rate matched FIFO function and my error counter is zero...I have yet to perform more testing, but so far so good. I do not have any TX/RX errors ( I am crossing my fingers as I type ). So for my case insofar I have not had the need for the Rate Matched FIFO. It is pretty cool that the PHY can detect such slight variations among the different modules...neat! Gotta love Altera for that...sorry INTEL :-P