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Yes the P in PLL stands for 'phase' but when a PLL locks to the phase of the input, this means it is also frequency locked (see the second paragraph of the Wikipedia PLL article, unfortunately I can't post the link).
Since the Rx-PLL will be frequency locked to the incoming data stream I still don't understand how any slippage/drifting can occur and why the rate-matching FIFO is needed.
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It is needed to decouple the processing of the incoming data stream which is in the recovered clock domain as you point out correctly, and the read side of the FIFO which is typically in a different clock domain different both in phase and frequency. The reason for rate-matching is because once you start processing the data typically in blocks, you do not want the processing to be interrupted by the read fifo going empty - it makes the pipeline design easier knowing that there is no "hole" in the incoming data. One could just stay in the recovered clock domain but then if the data goes away, the clock wanders of drifts and you may even get glitches leading to unpredictable behavior. So the read side clock is kept independent of the recovered clock. And of course, since the read side clock is independent you can imagine how slippage or drifting can occur. The short term frequency of the read clock can be made faster so as to prevent an overflow in the FIFO, but the problem is that it leads to the read fifo going empty and the pipeline needing to be designed to tolerate that. No harm, just more work. I hope this helps.
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