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The receiver's PLL locks to the incoming data rate so why does it matter if there are ppm differences in the reference clocks?
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PLL stands for
phase Locked Loop and not Frequency (i.e. data rate) Locked Loop.
It means the RX's PLL is able to counteract an improper phase shift between the incoming bit stream and the RX recovered local clock that would possibly lead to sample the data while it is changing (a Setup/Hold Time violation in other words).
Regarding the "ppm differences", this expression refers to small differences between the frequency of the data transmitter and the frequency of the data receiver (TX and RX data rates are different if you prefer). Now, imagine you are looking in the time domain at two bit streams that have a slight difference in their data rates. You will see that they are slowly sliding one relative to the other. More over, the more their data rates are different, the more they will slide rapidly. This is simply the visual traduction of the fact that a frequency difference between two signals means their phase difference is continuously and constantly increasing along with time.
Finally, if your incoming bit stream is continuously sliding with respect to the RX sampling clock, you will periodically skip one bit or more depending on the rate difference. Therefore, you need a time buffer(a FIFO) to avoid loosing some data bits and the more the data rates will be different, the deeper your FIFO will need to be, just as the deeper your bathtub will be, the later it will overflow if you forget to close the water tap ;)
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