Transceiver passthrough in Cyclone V

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I would need to be able to connect one Rx transceiver to any of the other Tx transceivers, dynamically. There would be multiple Rx receivers.

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Treat every transceiver interface as its own clock domain. Treat the FPGA as the multiplexing clock domain. Each transceiver has an RX and TX channel. The transceiver to FPGA core interface would use a dual-clock FIFO. The FIFO interfaces can be converted to use the AXi4-Stream or Avalon-ST stream protocols.

Your multiplexing logic operates in the FPGA core clock domain and simply routes AXI4-Stream/Avalon-ST traffic from each source to each destination.

Each transceiver block needs a reference clock. The FPGA core can use the same frequency, or a faster clock, or a slower clock (depending on the data volume). The clocks can all be identical frequencies if possible, but that is not a requirement. The FIFOs take care of clock-domain crossing, and the transceiver protocol needs to take care of idle character insertion and removal.

Simulate this and it will work just fine.

There are some basic transceiver and BFM examples here ...

https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html

Cheers,

Dave