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Altera_Forum
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14 years ago

Transceiver Clock Distribution in Stratix IV GX (1152-pin package) device

Hi everyone,

I'm currently working on a transceivers clocks routing solution, and I can't actually find the appropriate Clock Distribution figure in Altera documention. :(

Indeed, at page 22 of Altera's "Transceiver Clocking in Stratix IV Devices", we can see an example of Transceiver Clock Distribution for two devices.

The problem is that as the FPGAs I'm working on are not based on the same number of package pin, the chip architecture is not the same, and so must is it for the transceiver clock distribution.

So here is my question : Is there any documentation where I could find the appropriate figure for 1152-pin package based FPGAs ?

The exact devices are EP4SGX180HF35C2 and EP4SGX230HF35C2

Thank you so much for your help.

Have a nice day !

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    you might as the question at a higher level - what are you trying to do?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    Actually i'm working on a system which imposes me to work only with the transceivers at one side of the chip. The system is composed of three transceivers (two using 4 lanes (Basic transceivers) and one using 2 lanes (CMU PMA-direct)).

    The idea would be to have each one clocked at an independant high speed frequency.

    I would like to use the x4 and xN (bottom and top) clock lines, but I'm not sure about what I'm allowed to do or not, considering that I couldn't find the appropriate clock distribution figure for my FPGAs.

    Basicaly, the side of the chip i'm working on is devided into two transceivers blocks. So what I would like to try is, in each transceiver block :

    * one 4-lanes transceiver clocked by a local CMU0 PLL using the x4 clock line

    * using the remaining CMU available in each transceiver block as a PMA-direct lane of my 2-lane transceiver, and using the ATX PLL and the xN_bottom and xN_top to clock each one of these lanes with the same PLL

    I'm really not sure if I'm clear enough, it is kind of hard to explain... :p

    If anyone as any better idea to suggest, or simply think that I can't do what I'm explaing, it would be really appreciated to tell me.

    Thank you so much for your help !

    Regards
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Create altgx and altgx_reconfig components to do what you describe and let Quartus synthesis determine whether or not you can do what you describe.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Dave is right, in the end Quartus is the true test of what's legal. there are so many rules that need to be checked that i don't think you'll get the whole picture from documentation alone. the software can also enable things that were previously not allowed, so the document can be stale

    i understand this is a tedious approach
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi everyone,

    Thanks for these really helpful answers, because I think you're right, this is the best thing to do.

    I will stop trying to look at all the altera documentation I can find, because I will probably lose myself in all this stuff !!!! :p

    I will rely on Quartus to help me find the best solution.

    Thank you again, and have a nice day.

    Regards