Honored Contributor
Honored ContributorHi,
Actually i'm working on a system which imposes me to work only with the transceivers at one side of the chip. The system is composed of three transceivers (two using 4 lanes (Basic transceivers) and one using 2 lanes (CMU PMA-direct)). The idea would be to have each one clocked at an independant high speed frequency. I would like to use the x4 and xN (bottom and top) clock lines, but I'm not sure about what I'm allowed to do or not, considering that I couldn't find the appropriate clock distribution figure for my FPGAs. Basicaly, the side of the chip i'm working on is devided into two transceivers blocks. So what I would like to try is, in each transceiver block : * one 4-lanes transceiver clocked by a local CMU0 PLL using the x4 clock line * using the remaining CMU available in each transceiver block as a PMA-direct lane of my 2-lane transceiver, and using the ATX PLL and the xN_bottom and xN_top to clock each one of these lanes with the same PLL I'm really not sure if I'm clear enough, it is kind of hard to explain... :p If anyone as any better idea to suggest, or simply think that I can't do what I'm explaing, it would be really appreciated to tell me. Thank you so much for your help ! Regards
