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Hi Michael,
Read the Altera documentation on SOPC Builder (old tool) and Qsys (newer tool), and the Avalon bus specification.
What you want is an SOPC/Qsys system with an Avalon-ST ADC source, an SGDMA controller, an SRAM controller, and an Avalon-MM master (eg. the JTAG-to-Avalon-MM bridge or a NIOS II processor).
You will need to design the ADC to Avalon-ST streaming component (its pretty simple though). You can then use the SGDMA controller for Avalon-ST (ADC) to Avalon-MM (SRAM) data movement.
Cheers,
Dave
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Dave,
From your previous post, is a NIOS 2 processor an option in the design? cause you said "(eg. the JTAG-to-Avalon-MM bridge OR a NIOS II processor).". I thought NIOS 2 is used for commanding data movement?
For me to get some reassurance, do you think that this design will work on the DE2-115's SRAM at 65MHz? i need to know this before i dig deep into this, as i have limited time to work on this project.:(
Thank you.
Michael
Honored Contributor
