--- Quote Start ---
During the write burst operation, can i just keep WEN, CEN, OEN, UBN, and LBN low the whole time?
--- Quote End ---
No, you can't.
During a write-burst, you can keep chip-select asserted and the byte-enables asserted, but the write-enable signal (weN) needs to be pulsed. Writes to the SRAM occur on the rising-edge of write-enable. However, the SRAM writing timing requirements have timing parameters that are relative to both the falling-edge and the rising-edge of the write-enable pulse. Look at the SRAM data sheet, tSA = 0ns indicates that the address must be valid for no less than 0ns when write-enable asserts, and tHA = 0ns indicates that the address must be valid for no less than 0ns when write-enable deasserts. Given that the FPGA address clock-to-output timing is different than the write-enable clock-to-output timing, there is no way you can guarantee across all temperature variation that you can meet this timing by changing the address on the same clock cycle as you change the write-enable pulse, hence you must have a clock at the start, and a clock at the end, to ensure your FPGA controller meets the SRAM timing.
Cheers,
Dave
Honored Contributor
