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Note that tSA, tHA and tHD can be as low as zero. My interpretation is that even the UP and LB pulses shown are not needed, it suffices to keep them low during the write burst, along with CE, WE and OE.
And then, you only need to make sure tSD is respected relative to the next address change.
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During the write burst operation, can i just keep WEN, CEN, OEN, UBN, and LBN low the whole time? do i really need to pulse LBN and UBN ?
UBN = active low upper byte access
LBN = active low lower byte access
CEN= active low chip enable
WEN = active low write enable
OEN = active low output enable
Michael
Honored Contributor
