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From the user manual of Terasic, it says the SRAM has maximum performance of up to 125MHz under condition of standard 3.3V....
so i thought 1/125MHz = 8ns ?? no?
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You can't believe everything you read :)
Look at the timing diagram I posted, and compare it to the timing diagram in the SRAM data sheet. If the low time of sram_weN is adjusted to be exactly 8ns, then the actual low time of the FPGA pulse must be 8ns PLUS the clock-to-output uncertainties. Since the SRAM has setup parameters relative to the falling edge of write-enable and other timing parameters relative to the rising-edge of write-enable, you need an additional clock at either end.
The fastest you can run this SRAM is a 3 clock write cycle. If your clock is 125MHz, then your clock period is 8ns, but your write-enable low time would have to be two clocks to ensure you meet the 8ns low-time requirement of the SRAM. Hence, you have a 4 x 8ns = 32 ns write cycle, so your maximum write performance is 1/32ns = 125MHz/4 = 31.5MHz.
You could make the interface faster by using a clock higher than 125MHz, but you'd still be limited by the clock-to-output uncertainty of the FPGA outputs.
Cheers,
Dave
Honored Contributor
