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Honored Contributor
Honored ContributorTo build a FIFO using SRAM
Hi, I would like to build a DCFIFO using a SRAM chip on DE2-115. Any idea on where i should start? I know SRAM reads and writes on a different clock cycle as the dataIn and dataOut share t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I think we're misunderstanding each other! :D --- Quote End --- Yes, its always a possibility, lets see what you propose ... --- Quote Start --- What I'm proposing is a back to back write sequence such as: clk 0: WE = UB = LB = CS = OE = 0; ADDR = addr0; DATA=xxxx clk 1: ADDR = addr0; DATA=data0; others remain the same clk 2: ADDR = addr1; DATA=data1; others remain the same clk 3: ADDR = addr2; DATA=data2; others remain the same ... clk N: ADDR = addrN-1; DATA=dataN-1; others remain the same clk N+1: WE = 1; ADDR = addrN-1; DATA=dataN-1; others remain the same No complicated pulses on WE/CS/OE/UB/LB! --- Quote End --- Yeah, but no writes either :) The write-enable signal rising-edge is used for each and every write to the SRAM, and you need to meet the tHD = 0ns, and tHA = 0ns requirement, so you cannot change these signals for one clock. Let me attach a figure ... The figure was drawn for the slower SRAM on the BeMicro, however, its got much the same timing parameter names as the DE115 SRAM. Cheers, Dave
