To build a FIFO using SRAM

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http://www.issi.com/pdf/61wv102416all.pdf

Please take a look at write cycle number 4 in page 16.

Note that tSA, tHA and tHD can be as low as zero. My interpretation is that even the UP and LB pulses shown are not needed, it suffices to keep them low during the write burst, along with CE, WE and OE.

And then, you only need to make sure tSD is respected relative to the next address change.

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I was talking about the FPGA side of the interface.

The SRAM requirement is that tSA = 0ns and tHA = 0ns minimum be met, and you cannot guarantee this using FPGA I/O pins and asserting both the address and write signals all at the same time. Hence you need to assert the address/byte-enables/data one clock before the write-low pulse, and then deassert the controls one clock after. Or you can play tricks with rising and falling edges of the clocks. However, you need to know the clock-to-output delays of the FPGA before you can play those tricks.

Cheers,

Dave