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Honored Contributor

14 years ago

TMR in FPGA circuits against SEU

Can somedy help me to undarstand one thing?Does the triple modular redundant flip-flops in FPGA circuit mean that we change the structure of logic cell?

Altera_Forum

Honored Contributor

14 years ago

No, it means you use multiple logic elements to implement a single TMR FF.

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TMR in FPGA circuits against SEU

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