Tip/suppornt on debugging a VHDL project on Altera

Regarding sensitivity lists:

sensitivity lists are there for simulation purposes. Synthesisors ignore them, but will probably warn you when something it missing. They tells the simulator when to re-analyse the process. Any event on the signals in the sensitivity list trigger it.

This means that for a clocked process, because you only want outputs to change when the click rises, you only need to put clock in the sensitivity list. But if you wanted to build something like an asynchronous mux, you need to have all inputs in there:

process(s, s0, s1);
begin
  case s is
    when 0 => 
      output <= s0;
    when 1 =>
      output <= s1;
  end case;  
end process;

Here, you change output whenever s changes, but also if S=0, you need the change the ouput whenever s0 changes.

Now, if it was a clocked mux, you'd just have clock in there, because you only reasses "output" when the clock changes.

Now to your problems:

The problem with sampling clocks is that unless they are synchronised or related, they are most likely going to drift in and out of phase. So you could sample it at 0, or 1, or somewhere in between and get meta stability. Always use normal logic outputs in any other logic, never clocks or asynchronous signals.

As for your question about state machines - its up to you. If it's easier for other people (and yourself when you come back to this code in 6 months time) to understand whats going on, then do it.