Forum Discussion
paul26
New Contributor
New ContributorTiming violations while integrating 2 display port example designs..
Hi, I have generated an example design for display port which compiled successfully. As we are dealing with 2 display ports i made a second instantiation of the same example top. this time i got a t...
RichardT_altera
Super Contributor
Super ContributorWhen you report timing the failing slack, in the timing report, you can right-click the failing path, Set False Path(between nodes or clock). In this case, this seem to be clock-to-data analysis.
Select Set False Path (between clock) > Update Timing Netlist > Setup Summary. You will see the first timing violation has gone. Repeat the rest of the timing path violation (make sure to check whether the timing path can be false path.)
Best Regards,
Richard Tan
