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Altera_Forum's avatar
Altera_Forum
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17 years ago

Timing violations on SignalTap II Analyzer

Hi, I am receiving lots of timing violations on signals crossing clock domains to SignalTap II Analyzer. Should I set false path to all the signals connected to the SignalTap II analyzer? ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

As far as I know, the embedded logic analyser has one sampling clock. Hence there is no reliable way to sample data from different clk domains.

Intersting point...why altera doesn't add more sampling clocks?