CLinNew Contributor5 years agoTiming violated from user clock to EMIF phy clock issue Hi Intel, I got timing violated from emif_core_usr_clk to emif_phy_clk_l_1. Is it possible to set false path for emif_usr_clk to any emif_phy_clk? Show More
fishshineNew Contributor1 year agohello CLin,Have you solved the problem? I encountered the same problem.
Recent Discussionsadding signal to debug/signaltapSDM & Configuration InterfaceNeed Part EOL status(Active/Obsolete/Discontinued/NRND)Agilex 7 JTAG Config Fails at 1% on Board #2 (Error 18950 / CONF_DONE Low) - But Board #1 WorksECCN and HTS code for 1SX110HN2F43E2VG