Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Timing simulation

Hi, I'm having problems with timing simulation in Modelsim. I compile and sythesize in Precision and I do the map and route in Quartus. Once I have the .sdo, .vho and testbench files I tried t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

I have tried to find a solution but I'm not capable. The RTL simulation goes perfectly, the problem starts when I introduce the .sdo file. I continue with the same errors 

# ** Error: (vsim-SDF-3250) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(35): Failed to find INSTANCE '/testbench/iCLK_50_ibuf/asynch_inst'.
#  ** Error: (vsim-SDF-3250) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(44): Failed to find INSTANCE '/testbench/\iCLK_50~clkctrl\'.
#  ** Error: (vsim-SDF-3250) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(53): Failed to find INSTANCE '/testbench/\iCLK_50~clkctrl\/extena0_reg'.
#  ** Error: (vsim-SDF-3250) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(68): Failed to find INSTANCE '/testbench/\iSWITCH_ibuf_0_\/inreg_D3656_mux'.
#  ** Error: (vsim-SDF-3250) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(77): Failed to find INSTANCE '/testbench/\iSWITCH_ibuf_0_\/input_reg'.
#  ** Warning: (vsim-SDF-3432) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo: This file is probably applied to the wrong instance.

I thinks that the problem is that I don't give the correct path to the instance, as this links comments: http://www.altera.com/support/kdb/solutions/rd05152000_7434.html. I tried to show the path in : SDF--> APPLY TO REGION showing the .vho file.

Anyone can suggest me the correct way to do this

Many thanks