Altera_Forum
Honored Contributor
16 years agotiming requirements not met, but design works
Hello everybody,
I have been testing my system and everything seems to be ok. I am processing one image, and the output is what I expected. However the classic timing analyzer said me that the "Total number of failed paths is 1069". What does it means? I am using one PLL that receives a 24MHz signal, and generate one 160MHz clock. (I suppose that because I am using this PLL, Quartus knows about the frequency) I am using Cyclone 2 speed grade 8. Thank you.