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What does it means?
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Assuming the timing analysis parameters are basically correctly describing your design, it means, your design may operate incorrect under particular conditions, e.g. higher temperature, supply voltage at the lower tolerance band, individual device variations. Each path failure should be inspected and corrected somehow.
You may have a lock at the negative slack reported for failed paths to judge the respective severity. If it's rather low, e.g. below 0.5 ns, the timing failure most likely won't show up. But it's not O.K. anyway.
A general method to take the edge of a critical timing is adding pipelining registers to a data path, if applicable. As a first step, you should try to understand where the timing bottleneck of your design is located.
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