Timing problems, Help

Jose. As Rysc is trying to indicate, you need to provide more information about the design. Did you synthesize and fit each of the blocks seperately to get the fmax results you're indicating? Where are you getting your numbers from?

Again, as Rysc has indicated, the overall fmax of the system depends not only on the fmax of the slowest block but how the blocks are connected together.

What you need to do is focus on the combined system rather than the individual blocks. Look at the top failing paths for the system to determine what is failing. Why they are failing will probably be immediately obvious.

Jake

:)

40MHz? From your analysis, is your failing path setup, hold, recovery or removal(I'll assume setup since you talk about Fmax, but Fmax is a limited term when it comes to static timing analysis.) That is based on the worst case path in your design. When you did an analysis of this path, were your launch and latch clocks the same? What's the setup requirement? What was the clock skew? What was the datapath, and if it's 25ns, how many levels of logic? What device and speed grade? If you provide that info, we might be able to diagnose the problem, or at least have enough info to ask more questions, but the information so far is too limited to really provide an answer.

uhhmmmm...

fmax of cordic block = 200Mhz

fmax of 18 bits counter = 210Mhz

cordic + counter = 40 Mhz (when they are connected) and I need 150Mhz !!!! <--- This is the problem

If I understand correctly, your system Fmax is now 200MHz, i.e. the slowest path in your system. (Your cordic probably has some paths that run much faster than 200MHz, but timing analysis is based on the slowest path, no matter how many paths there are.)

Also, if you're analyzing these two separately, don't just assume hooking them up will give the same results. Expect a little degradation as you fill up the device. (Or a lot, depending on how cautious you want to be, how much you plan on filling it up, and "how" your design fills up...)