Timing problems, Help

:)

40MHz? From your analysis, is your failing path setup, hold, recovery or removal(I'll assume setup since you talk about Fmax, but Fmax is a limited term when it comes to static timing analysis.) That is based on the worst case path in your design. When you did an analysis of this path, were your launch and latch clocks the same? What's the setup requirement? What was the clock skew? What was the datapath, and if it's 25ns, how many levels of logic? What device and speed grade? If you provide that info, we might be able to diagnose the problem, or at least have enough info to ask more questions, but the information so far is too limited to really provide an answer.