Forum Discussion
Honored ContributorTiming problems, Help
Hi, I designed a cordic block that has a fmax of 200 Mhz and I have a 18 bits counter that provides the angle for cordic block, this counter has a fmax of 210 Mhz. Here I don't have problems, but when I connect both the fmax is 40 Mhz and I need 150 Mhz !!!!
Do you have an idea to improve the fmax? Is it necessary to rebuild the blocks? Thanks.14 Replies
Altera_ForumAs Rysc and I said, you must pipeline the cordic processor.
- Altera_Forum
according this line
Info: - Longest register to register delay is 23.123 ns There is a combinational block that must be Checked . Look for this block and optimize it. (adder?). Add pipelining registers to improve the performance. - Altera_Forum
OKay. The counter is naturally no problem, as it's output is a register. Coming into the cordic(U2), there is a path that is 40 levels of logic. I think the only thing that will fix this is pipelining, i.e. adding registers along this path, which will increase your latency. Going down the path, you go through several hierarchies, u0, u1, u2, u4 and u6, so probably the most logical thing to do is add registers between these hierarchies. (If this is just dataflow, it's pretty straightforward. If any of these blocks loopback into the datapath, it gets much more complicated as you need to balance pipelining so all data lines up.)
The reason this never showed up in an Fmax report is that when compiled by itself, it came from an input pin and so wasn't analyzed as part of Fmax(which is generally considered register to register, and part of the reason Fmax is a limited picture). For higher speed designs, and 150MHz is getting up there, you need to consciously pipeline throughout your code. Finally, and I almost fear bringing it up, if you go to Tools -> Advisors -> Timing Optimization Advisors, there are some suggestions to help you move the levers/settings in Quartus to get better results. Bottom line is I don't think any of them will help you get the improvements you need, and I worry about relying on these too much(I assume you're early in the design, so as you add more logic it becomes more and more difficult), but they could be useful AFTER you modify the code and get it much closer, if you need to tweak out some more. It depends on the critical path, though. - Altera_Forum
ok, ..... here the file
- Altera_Forum
Can you do a right-click on the first path and then a List Path. The path details will be broken out below(you can open and close them with the +/- buttons on the left). Then cut and paste all the information into a text file. This is just summary information and doesn't provide enough detail. (Although my original assumptions seem wrong, as I was expecting a clock path issue. You may have a really long datapath, although I can't know for sure without the details.)
- Altera_Forum
Ok, Here are the files... the problem is in "clock setup".
- Altera_Forum
If you're using the Classic Timing Analyzer, go to the failing setup panel, right-click on the worst case path and do List Paths. The path details will be broken out below. Cut and paste this into a text file and then attach it. That will provide a lot more information we can help with. There are probably a hundred tips and tricks, if not more, most of which won't apply. Being able to analyze a single path and use that as a starting point toward the root cause is an invaluable skill.
- Altera_Forum
Ok, thanks to all......
I'm beginner, really I never think it all this parameters that you say, now I'm learning with your comments about the cautions with connection between blocks, paths, etc. The fmax is a data from Quartus II timing Analyser. Can you say me general "techniques" or "tricks" to improve the operation frequency or texts to red about it ? Thanks for your help. - Altera_Forum
Hi Jose
I assume you run separate projects for your Counter and Cordic ? With the timing "Fmax" you only get the paths between the registers, but your designs has also paths from input pins to registers (tsu) and paths from register to output pins (tco). When you analyze your projects you have to keep in mind that some outputs will be connected to inputs of the other project. These pahts needs to be checked also. - Altera_Forum
Try adding pipelining registers between the combinational blocks of the cordic processor. if you did not use them.
You should register all the inputs and outputs.
