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Altera_Forum
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7 years ago

Timing failure on internal paths

Hi dear, The design failing the time on internal paths and on the same clock domain. The timing report is attached as image . This design works fine without any constraints. Can p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi,

Thank you for your reply,

I have not written the design, the person who have written this code is retired now. I have written a short description of the design attached as pdf file and also the constraints which I have written are also attached.

I want to increase the speed / frequency of algorithm. The algorithm in design is working fine at 164MHz clock without any constraints and I was able to run it at 190MHz with the attached constraints.

Please let me know if you need further information.