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Altera_Forum
Honored Contributor
Honored ContributorTiming failure on internal paths
Hi dear, The design failing the time on internal paths and on the same clock domain. The timing report is attached as image . This design works fine without any constraints. Can p...
Altera_ForumHonored Contributor
Honored ContributorLooks like you have a large fan-out path thats causing the timing violations. In any case, can you describe what you're designing and also put in the constraints etc here so we can take a look at it.
