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Altera_Forum
Honored Contributor
Honored ContributorTiming failure on internal paths
Hi dear, The design failing the time on internal paths and on the same clock domain. The timing report is attached as image . This design works fine without any constraints. Can p...
Altera_ForumHonored Contributor
Honored ContributorWithout seeing your design or clock constraints makes it difficult to help.
The picture shows a long data delay so perhaps you have too much logic on those paths. No way to know for sure.
