Timing Error with RGMII Ethernet on CycloneV SoC

Question

I want to solve the timing error message.

Design : Cyclone V RGMII Example Design

Setup Timing error path : TX_CLK_OUT_125

I am trying the below( 9 paths);

It is look like timing violation.

I want solve timing error. Please tell me about solve it.

If anyone has any idea, please tell me.

Thanks in advance.

mingyuexin · Answer

Have you solved this issue? I have the same timing violation and could not solve it.

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