Timing constraints to use with EPCQ128A on Cyclone10 LP Evaluation Board

Hi,

The signal delay from FPGA or flash memory device to the PFL synchronous input port is specified by set_input_delay. The delay calculation is:

Input delay value = Board delay from FPGA or flash output port to the PFL input port + TCO of the FPGA or flash memory device

The signal delay from PFL synchronous output port to FPGA or flash memory device is specified by set_output_delay. The delay calculation is:

Output delay value = Board delay from the PFL output port to the FPGA or flash input port + TSU of FPGA or flash device.

Reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf Chapter 1.4.2.2. Constraining Synchronous Input and Output Ports

Thanks.